EDN

DRAM basics and its quest for thermal stability by optimizing peripheral transistors

For decades, compute architectures have relied on dynamic random-access memory (DRAM) as their main memory, providing temporary storage from which processing units retrieve data and program code. The ...
Nasdaq

SK hynix Presents Future DRAM Technology Roadmap at IEEE VLSI 2025

SEOUL, South Korea, June 9, 2025 /PRNewswire/ -- SK hynix Inc. (or "the company", www.skhynix.com) announced today that it presented a new DRAM technology roadmap for the next 30 years and the ...
Semiconductor Engineering

Baby Steps Toward 3D DRAM

Flash memory has made incredible capacity strides thanks to monolithic 3D processing enabled by the stacking of more than 200 layers, which is on its way to 1.000 layers in future generations.[1] But ...
TweakTown

Samsung teases 16-layer 3D DRAM with VCT DRAM as a 'stepping stone' for future RAM

VCT (vertical channel transistor) DRAM is one of the first achievements towards this goal, with Samsung expected to complete the initial development of VCT DRAM in 2025, with 3D DRAM hitting the ...
Semiconductor Engineering

DRAM Microarchitectures And Their Impacts On Activate-Induced Bitflips Such As RowHammer

A technical paper titled “DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands” was published by researchers at Seoul National University and University of ...
EDN

0.4-V DRAM array technology using twin cells for next generation mobile devices

Hitachi, Ltd. (NYSE: HIT / TSE: 6501) in cooperation with Elpida Memory, Inc. (TSE: 6665), have proposed a new DRAM(*1) circuit design enabling 0.4-V operation. The proposed array employs a twin cell ...
TechSpot

DRAM manufacturers explore new designs to overcome 3D stacking hurdles

Something to look forward to: The memory industry is known for its conservative approach, often favoring incremental improvements over revolutionary changes. But as we look toward the end of the ...