Business Wire

Aldec Adds VHDL Standard 1076-2018 Extensions and Automatic Coverage Model Generation to Riviera-PRO™

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., an industry leader in electronic design verification, has added VHDL-2018 interfaces and automatic coverage model generation to its Riviera-PRO™ advanced ...
New Electronics

Aldec adds UVM Generator to Riviera-PRO

Aldec, a specialist in mixed HDL language simulation and hardware-assisted verification for FPGA, ASIC and SoC designs, has added an automatic UVM Generator function to Riviera-PRO. The addition is ...
EDN

Aldec Brings Mixed VHDL/Verilog/SystemC Verification to Mainstream Designers

Aldec, Inc., announced the release of Riviera 2004.08 with a direct simulation kernel connection with SystemC, creating a highly efficient system-level co-simulation environment for next generation ...
Business Wire

Aldec and SynthWorks Deliver Randomization and Functional Coverage Capabilities to VHDL Designers with OS-VVM™

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., in collaboration with SynthWorks Design Inc., today announces the availability of Open Source - VHDL Verification Methodology (OS-VVM™), underscoring the ...
New Electronics

Aldec enhances Active-HDL to support new features

Aldec, a specialist in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has announced that it has enhanced Active-HDL to support new features within ...
Design-Reuse

Aldec Releases Integrated SystemC Debugging Environment with Assertion-Based Verification

Henderson, Nevada - December 27, 2004-- Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced the release of Riviera 2004.12. The new ...
EDN

Aldec FPGA simulation added to Altium Designer

Altium and Aldec have signed an OEM agreement that adds Aldec's FPGA simulation capabilities to Altium Designer. Electronics designers can now access Aldec's VHDL and Verilog simulation technology as ...