Design-Reuse

A Re-Usable Level 2 Cache Architecture

This paper presents the architecture of a high performance level 2 cache capable of use with a large class of embedded RISC cpu cores. The cache has a number of novel features including advanced ...
The Next Platform

Cache Is King

The gap between the performance of processors, broadly defined, and the performance of DRAM main memory, also broadly defined, has been an issue for at least three decades when the gap really started ...
Design-Reuse

Adding Cache to IPs and SoCs

• Cache memory significantly reduces time and power consumption for memory access in systems-on-chip. • Technologies like AMBA protocols facilitate cache coherence and efficient data management ...
Semiconductor Engineering

Cache Occupancy Attacks Targeting The SLC of Apple M-Series SoCs (Northeastern Univ.)

A new technical paper titled “EXAM: Exploiting Exclusive System-Level Cache in Apple M-Series SoCs for Enhanced Cache Occupancy Attacks” was published by researchers at Northeastern University. “Cache ...