Semiconductor Engineering

Understanding UVM Coverage For RISC-V Processor Designs

This white paper focuses on the first technique in this list. It explains the basics of UVM functional coverage for RISC-V cores using the Google RISCV-DV open-source project, Synopsys verification ...
EDN

VCS commands ease coverage efforts & speed simulation

This blog talks about challenges and solutions while reusing the required functional coverage of IP at the SoC level, coverage merging issues, exclusion/removal of groups from functional coverage ...
Semiconductor Engineering

Universal Verification Methodology Coverage For Bluespec RISC-V Cores

Attempting to achieve complete RISC-V verification requires multiple methodologies, one of which is coverage driven simulation based on UVM constrained random methods and complaint with the Universal ...
Design And Reuse

DDR Verification Challenges in Modern Chip Design

That’s the reality of modern DDR verification. Double Data Rate (DDR) memory interfaces are fundamental to modern SoC and ASIC designs, enabling high-bandwidth communication between processors and ...