EDN

SoC design verification tool aids productivity

The Questa Verification Platform lets mainstream SoC designers more easily perform exhaustive formal verification analysis. The packages AutoCheck technology delivers fully automated formal checking ...
Semiconductor Engineering

Overview Of Security Verification Methodologies for SoC Designs Pre-Silicon (U. of Florida)

A technical paper titled “A Survey on SoC Security Verification Methods at the Pre-silicon Stage” was recently published by researchers at University of Florida. “This paper presents a survey of the ...
EDN

Network on Chip Router(ASIC) (SOC design)

Implemented a NoC Router in Verilog HDL. An exhaustive testbench was written and the design was tested against it. (Soc design flow – logic simulation, synthesis, timing analysis, verification). An ...