For decades, process and design scaling has triggered the adoption of transformative test solutions. About twenty years ago, when at-speed test became a de-facto requirement, on-chip compression ...

Bus-based packetized scan data decouples test delivery and core-level DFT requirements so core-level compression configuration can be defined completely independently of chip I/O limitations. Grouping ...

IC designers now have a powerful weapon in the struggle against rising test costs: commercially available EDA solutions that provide fast and effective means to implement scan compression on-chip. By ...

For more than four decades, scan technology has somehow eluded the radar screen of the IC test industry. As test continues to evolve and make significant newsworthy changes, scan has maintained a ...

Maybe you should try boundary scan testing now that your continuity buzzer has died. Most engineers are familiar with the theory of boundary scan testing, but what about having actual hands-on ...

With increasing numbers of ASICs finding their way into high-volume products, production testing of these devices must be fast, complete, trouble-free, and economical. To achieve these goals, ...