New Electronics

Microchip releases C++ synthesis suite for PolarFire FPGA algorithm development

Microchip Technology has added an HLS design workflow, called SmartHLS, to its PolarFire FPGA families to allow C++ algorithms to be directly translated to FPGA-optimised Register Transfer Level (RTL) ...
EDN

Tool develops FPGA algorithms from C/C++

CoDeveloper FPGA design tool allows algorithms to be developed and debugged with existing C/C++ tools. The tool helps identify dataflow bottlenecks, generates debugging visualizations for ...
EDN

Targeting Floating-Point Algorithms for FPGA or ASIC Deployment

Native Floating-Point HDL code generation allows you to generate VHDL or Verilog for floating-point implementation in hardware without the effort of fixed-point conversion. Native Floating-Point HDL ...
Nature

Hardware Architecture for Cryptographic Algorithms on FPGA

Field Programmable Gate Arrays (FPGAs) have emerged as a versatile platform for implementing cryptographic algorithms, offering a balance between flexibility, performance and energy efficiency. Recent ...
Nature

High-Performance Sorting Algorithms and Architectures Using FPGA

Field-programmable gate arrays (FPGAs) offer a unique platform for the implementation of high-performance sorting algorithms by combining inherent parallelism with customisable hardware architectures.
Electronics Weekly

C++ synthesis suite for PolarFire FPGA algorithm development

Microchip has released a C++ algorithm high-level synthesis design workflow for its PolarFire FPGAs. “A large majority of edge compute, computer vision and industrial control algorithms are developed ...