Electronic Design

How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers (Part 2)

This is Part 2 of a three-part series. As discussed in Part 1 and recapped here, modern wireless communications systems (mainly superheterodyne radio transceivers) are now required to deliver higher ...
EDN

Tutorial on PLLs: Part 2

The MAP estimator form is used for the estimation of random parameters whereas the maximum-likelihood (ML) form is generally associated with the estimation of deterministic parameters. From Bayes Rule ...
EDN

Jitter attenuation 101: How do you pick the right PLL bandwidth?

Clock signals provide reference timing to every integrated circuit and electrical system. While consumer applications typically use simple quartz crystals for reference-clock generation, other ...
Electronic Design

How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers (Part 3)

A special technique produces very wide loop BWs in high-frequency PLLs (and hence, indirect (PLL) synthesizers), thereby achieving very low phase noise rivaling that of direct (MMD) synthesizers. A ...